This page describes the proposed IDE hard disk interface. The IDE specification is simpler than SCSI so has been chosen for the prototype. The IDE interface would be almost trivial but for the fact that the IDE databus is 16 bits wide, whereas the eZ80 data bus is only 8 bits wide. It is possible to connect only 8 bits of the IDE bus directly to the eZ80 data bus, but doing this sacrifices half the capacity of the disk drive.

The solution here is to buffer the high byte of the data word in an 8-bit latch, which is read/written to on an additional port number. There are a number of examples of this on the internet, with circuit diagrams and sample code (see list of links below). The information and circuit described here are derived from these project pages. Below is the draft circuit diagram.

The IDE registers are mapped to eZ80 I/O addresses in the range &0020 to &002F. The high byte is written or read on port &0028. When writing a byte, the high byte register must be written prior to writing the low byte (&0020) so that it is available for sending to the disk drive, which occurs on writing to &0020. Similarly, reading from port &0020 reads the low byte and latches the high byte from the disk drive, which can then be read from port &0028.

CPC NG I/O Addresses for IDE Registers

The following table describes the port mapping of the IDE interface:

IDE Project Links

These are links to IDE projects with circuit diagrams, information, sample code and more.

IDE Register descriptions

This section describes the IDE register useage.

&0021 (write): Write Precomp: A write to this port sets the "Write Precompensation Cylinder divided by 4". Not sure what this means.

&0021 (read): Error Register: The contents of the error register when in diagnostic mode are shown in this table:

The contents of the error register (read &0021) when in operation mode are shown in this table:

&0026: Drive/Head: Bit 4 of the drive/head register selects drive 0 or drive 1, and bits 3-0 select the head.

&0027 (read): Status: Bits in the status register are set to 1 to indicate one of the following conditions:

&0027 (write): Command: Writes to the command register are as follows: